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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
FEATURES
* 6 LVCMOS/LVTTL outputs * Crystal oscillator interface * Output frequency range: 53.125MHz to 125MHz * Crystal input frequency: 25MHz and 25.5MHz * RMS phase jitter at 106.25, using a 25.5MHz crystal (637KHz to 10MHz): 3.25ps * Phase noise: Offset Noise Power 100Hz ................. -100 dBc/Hz 1KHz ................. -115 dBc/Hz 10KHz ................. -125 dBc/Hz 100KHz ................. -127 dBc/Hz * 3.3V core, outputs may either be 3.3V, 2.5V or 1.8V * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS84025 is a Crystal-to-LVCMOS/LVTTL Frequency Synthesizer with Fanout Buffer and HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The VCO frequency is programmed in steps equal to the value of the crystal frequency. The VCO and output frequency can be programmed using the feedback and output frequency select pins. The low phase noise characteristics of www..com the ICS84025 make it an ideal clock source for Fibre Channel 1 and Gigabit Ethernet applications.
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FUNCTION TABLE
Inputs MR 1 0 0 0 0 F_SEL1 X 0 0 1 1 F_SEL0 X 0 1 0 1 25.5MHz 25.5MHz 25MHz 25MHz XTAL Output Frequency F_OUT LOW 53.125MHz 106.25MHz 62.5MHz 125MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
VDDO Q0 GND Q1 VDDO Q2 GND Q3 VDDO Q4 GND Q5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 F_SEL0 F_SEL1 MR XTAL1 XTAL2 GND VDDA VDD PLL_SEL GND nc VDDO
XTAL1
OSC
XTAL2
0 1
Output Divider
6
/
Q0:Q5
PLL
Feedback Divider
ICS84025
24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View
F_SEL1 PLL_SEL MR F_SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84025EM
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Type Power Output Power Output Output Output Output Output Unused Input Power Power Input Input Pullup Description Output supply pins. Clock output. LVCMOS/LVTTL interface levels. Power supply ground. Clock output. LVCMOS/LVTTL interface levels. Clock output. LVCMOS/LVTTL interface levels. Clock output. LVCMOS/LVTTL interface levels. Clock output. LVCMOS/LVTTL interface levels. Clock output. LVCMOS/LVTTL interface levels. No connect. Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. Core supply pin. Analog supply pin. Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the Pulldown internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Pullup Output frequency select pin. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 5, 9, 13 2 3, 7, 11, 15, 19 4 6
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Name VDDO Q0 GND Q1 Q2 Q3 Q4 Q5 nc PLL_SEL VDD VDDA XTAL2, XTAL1 MR
10 12 14 16 17 18 20, 21 22
23 24
F_SEL1 F_SEL0
Input Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V VDD = 3.465V, VDDO = 1.95V 51 51 TBD TBD TBD Test Conditions Minimum Typical Maximum 4 Units pF K K pF pF pF
84025EM
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 46.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
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TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 1.65 Typical 3.3 3.3 3.3 2.5 1.8 71 15 70 Maximum 3.465 3.465 3.465 2.625 1.95 Units V V V V V mA mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current PLL_SEL, MR, F_SEL0, F_SEL1 PLL_SEL, MR, F_SEL0, F_SEL1 MR, F_SEL1 PLL_SEL, F_SEL0 MR, F_SEL1 PLL_SEL, F_SEL0 Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO = 3.3V 5% VOH Output High Voltage; NOTE 1 VDDO = 2.5V 5% VDDO = 1.8V 0.15V VDDO = 3.3V 5% VOL Output Low Voltage; NOTE 1 VDDO = 2.5V 5% VDDO = 1.8V 0.15V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section, "Output Load Test Circuit" diagrams. -5 -150 2.6 1.8 VDDO- 0.45 0.5 0.5 0.45 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V V V V V V
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance
84025EM
Test Conditions
Minimum 25
Typical Maximum 25.5 70 7
Units MHz pF
REV. A APRIL 16, 2003
Fundamental
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Test Conditions Minimum 53.125 50 TBD 20% to 80% 300 50 tPERIOD/2 - TBD tPERIOD/2 + TBD 700 Typical Maximum 125 Units MHz ps ps ps % ps
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter; NOTE 2 Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle Output Pulse Width
tjit(cc) tsk(o)
tR / tF odc
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PW
PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 2 Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle Output Pulse Width tPERIOD/2 - TBD 20% to 80% 300 50 tPERIOD/2 + TBD Test Conditions Minimum 53.125 30 TBD 700 Typical Maximum 125 Units MHz ps ps ps % ps
tjit(cc) tsk(o)
tR / tF odc tPW
PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.15V, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter; NOTE 2 Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle Output Pulse Width tPERIOD/2 - TBD 20% to 80% 300 50 tPERIOD/2 + TBD Test Conditions Minimum 53.125 30 TBD 700 Typical Maximum 125 Units MHz ps ps ps % ps
tjit(cc) tsk(o)
tR / tF odc tPW
PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
84025EM
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TYPICAL PHASE NOISE
0 -10 -20 -30 www..com -40 -50
25MHz Input
RMS Phase Noise Jitter 12K to 20MHz = 3.5ps (typical)
PHASE NOISE
-60
(dBc) HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 10 100
125MHz 62.5MHz
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
0 -10 -20 -30 -40 -50
25.5MHz Input
RMS Phase Noise Jitter 12K to 20MHz = 3.5ps (typical)
PHASE NOISE
-60
()
dBc HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 10 100
106.25MHz 53.125MHz
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
84025EM
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD, VDDA, VDDO = 1.65V5% 2.05V5% 1.25V5%
SCOPE
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VDD VDDO
Qx
SCOPE
LVCMOS
Qx
LVCMOS
GND = -1.65V5%
GND = -1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.4 0.9V 0.9V0.075V
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD VDDO
Qx
SCOPE
V
DDO
Qx
2
LVCMOS
V
DDO
Qy
2 tsk(o)
GND = -0.9V0.075V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
V V V
OUTPUT SKEW
VOH
DDO
DDO
DDO
Q0:Q5
2
2
2
VREF VOL
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
V
DDO
Q0:Q5
Pulse Width t
PERIOD
odc =
t PW t PERIOD
odc, tPW & tPERIOD
84025EM
2
tcycle
tcycle
n+1
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
Period Jitter
80%
80%
20% Clock Outputs t
R
20% t
F
OUTPUT RISE/FALL TIME
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84025 provides separate power supplies to isolate any high switching www..com noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10 F 24
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode operation. The ICS84025 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3.
20 C1 18pF 25MHz X1 21 C2 22pF
XTAL2
XTAL1 ICS84025
Figure 3. CRYSTAL INPUt INTERFACE
84025EM
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible.
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS84025. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 is 22pF and 18pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is
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VDD 13 14 15 16 17 18 19 20 21 22 23 24 U1 R6 R7 10 PLL_SEL VDDA 22p C11 0.1u C16 10u C1 X1 25MHz,18pF C2 43 18p VDD RU2 1K RU3 1K RU4 1K PLL_SEL F_SEL1 F_SEL0 ICS84025 F_SEL1 F_SEL0 VDDO NC GND PLL_SEL VDD VDDA GND XTAL2 XTAL1 MR F_SEL1 F_SEL0 Q5 GND Q4 VDDO Q3 GND Q2 VDDO Q1 GND Q0 VDDO 12 11 10 9 8 7 6 5 4 3 2 1 43 VDD Zo = 50
Zo = 50 R1
SP = Spare, Not Installed VDD=3.3V
(U1,1) VDD (U1,5) C5 0.1u (U1,9) C3 0.1u (U1,13) C4 0.1u (U1,17) C7 0.1u
RD2 SP
RD3 SP
RD4 SP
C6 0.1u
FIGURE 4A. ICS84025 SCHEMATIC EXAMPLE
84025EM
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
* The differential 50 output traces should have the same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
POWER
AND
GROUNDING
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Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 21 (XTAL1) and 20 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
C4
GND VDD VIA
C16 C11 VDDA R7
R6
50 Ohm traces
R5
50 Ohm traces
C3
50 Ohm traces
C1
C7
R4 R3
50 Ohm traces
C5 X1 R2 R1 C2 C6
50 Ohm traces 50 Ohm traces
U1
FIGURE 4B. PCB BOARD LAYOUT FOR ICS84025
84025EM
PIN1
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
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qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84025 is: 2949
84025EM
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REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
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TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 24 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119 www.icst.com/products/hiperclocks.html
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84025EM
REV. A APRIL 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Marking ICS84025EM ICS84025EM Package 24 Lead SOIC 24 Lead SOIC on Tape and Reel Count 30 per tube 1000 Temperature 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS84025EM ICS84025EMT
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84025EM
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REV. A APRIL 16, 2003

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